1. Field
Disclosed subject matter is in the field of integrated circuit design and, more particularly, the verification of an integrated circuit design using static timing analysis.
2. Related Art
In the design of integrated circuits, static timing analysis is performed to achieve a comparatively accurate and relatively quick assessment of a design's timing. In static timing analysis, timing characteristics assigned to standard cells are used to verify the design and identify critical timing paths. The characteristics and performance of a standard cell may, however, vary over time. These time dependent variations may be referred to generally as aging effects.
Known aging effects include, as examples, negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), and hot carrier injection (HCI) effects. NBTI produces damage to PMOS transistors and shifts PMOS threshold voltage upward. The extent of NBTI is influenced by voltage, temperature, and the state profile of the applicable PMOS device, where the state profile refers to the percentage of clock cycles a design spends in any given state. PBTI impacts NMOS transistors and, although not as significant as NBTI historically, may become more pronounced with advancing technology. HCI effects refer to damage from high switching current and depend on voltage and steady state current drive as well as the amount of switching that occurs.